1. Field of the Invention
The present invention relates to a memory device in a computer system, and more specifically, to a burst address sequence generator for addressing a static random-access-memory (SRAM) device.
2. Description of Prior Art
A synchronous SRAM device is generally utilized as a cache memory in a microcomputer system. In order to access data in the cache memory, an address sequence generator has to be provided in the microcomputer system to generate address sequences, called burst addresses. The burst address sequences have a format in conformity with the operating mode of a microprocessor of the computer system. Since there are at least two operating modes for a commercial microprocessor, the burst address sequences have to be provided with two formats, including an interleaved format and a linear format. Therefore, the burst address sequence generator should be controlled by a mode signal to generate both the interleaved and linear burst address sequences.
The interleaved burst addresses, if initialized, have the formats shown in Table 1.
TABLE 1 ______________________________________ 1st address 2nd address 3rd address 4th address (external) (internal) (internal) (internal) ______________________________________ X . . . X00 X . . . X01 X . . . X10 X . . . X11 X . . . X01 X . . . X00 X . . . X11 X . . . X10 X . . . X10 X . . . X11 X . . . X00 X . . . X01 X . . . X11 X . . . X10 X . . . X01 X . . . X00 ______________________________________
The formats of the linear burst address sequences are shown Table 2.
TABLE 2 ______________________________________ 1st address 2nd address 3rd address 4th address (external) (internal) (internal) (internal) ______________________________________ X . . . X00 X . . . X01 X . . . X10 X . . . X11 X . . . X01 X . . . X10 X . . . X11 X . . . X00 X . . . X10 X . . . X11 X . . . X00 X . . . X01 X . . . X11 X . . . X00 X . . . X01 X . . . X10 ______________________________________
A conventional burst address sequence generator has been disclosed in U.S. Pat. No. 5,319,759. The conventional burst address sequence generator includes a counter and a latch. However, the prior art circuit structure may be too complicated to be implemented in a semiconductor very large scale integrated (VLSI) circuit.